library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity chk_zero is
generic (N : integer := 32);
port(	data_in	: in std_logic_vector (N-1 downto 0);
		is_zero	: out std_logic
	);
end chk_zero;

architecture Structural of chk_zero is
begin

is_zero     <= '1' when to_integer(unsigned(data_in)) = 0 else '0';

end Structural;

